Wednesday, April 10, 2019

RISC-V

RISC-V is an exciting new microprocessor ISA (instruction set architecture).  In the last 30 years several proprietary ISAs have tried to dislodge x86 as the defacto processor standard with varying degrees of success.  ARM, MIPS, PowerPC, PA-RISC, SPARC, Itanium to name a few.  ARM has come closest to dominating the embedded space, but seems to have stalled lately.  But these are all proprietary which has something to do with the acceptance as a standard for the lowest level computer language.  Who wants to depend on a language owned by somebody else ?

A few years ago OpenRISC entered the market, but it's ecosystem and architecture are limited, largely due to the limited resources of the authors.  Enter RISC-V.  This architecture is very clean, well designed, open, and originally out of Berkeley.  This architecture is tracking to do for microprocessor architectures, what Linux did for Unix Server Operating Systems.

This architecture is going to run because it:
  • Has a very clean well designed extendable ISA
  • Easily emulates on x86
  • Completely open royalty free, with mechanisms for proprietary extensions
  • High performance free simulators already available
  • Huge list of technology companies already endorsing this architecture
  • Real silicon designs available today ready to be customized as desired.
Very cool.  This will open new frontiers in machine languages as well once it is no longer owned by some for profit company.

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